(i) Field of the Invention
The present invention relates to a semiconductor integrated circuit for outputting a voltage in accordance with a voltage difference between two data lines (for example, bit lines) and aims at a circuit used for a sense amplification circuit and the like such as an SRAM (Static Random Access Memory).
(ii) Related Background Art
In a memory such as an SRAM, data read from a memory cell through a bit line is amplified by a sense amplifier and then outputted.
FIG. 15 is a circuit diagram of a conventional sense amplifier. The illustrated sense amplifier includes: a flip flop composed of PMOS transistors Q1 and Q2 and NMOS transistors Q3 and Q4 for latching a voltage in accordance with a voltage difference between a pair of bit lines; an NMOS transistor Q5 for switching whether source terminals of the NMOS transistors Q3 and Q4 are set to a ground voltage; PMOS transistors Q6 and Q7 for switching whether voltages of bit lines BL and BLB are fetched to the flip flop; a PMOS transistor Q8 for equalization; and PMOS transistors Q9 and Q10 for pre-charging.
By turning on the NMOS transistor Q5, a very small voltage difference between a pair of bit lines BL and BLB is amplified by the flip flop and outputted from terminals SA and SAB (nodes S and SB).
Further, when the PMOS transistors Q8, Q9 and Q10 for equalization and pre-charging are in the ON state, the flip flop does not perform the latch operation, and both the nodes S and SB are pre-charged to the high level. When carrying out pre-charging, the NMOS transistor Q5 is turned off so as to prevent a passing electric current from flowing to the flip flop.
The respective transistors Q1 to Q4 composing the flip flop do not necessarily have the same characteristic and it is often the case that these transistors may have different threshold values. Assuming that the threshold values of the PMOS transistor Q1 and the NMOS transistor Q4 are shallow while the threshold values of the PMOS transistor Q2 and the NMOS transistor Q3 are deep, the node S of the flip flop is apt to become the high level, and the node SB tends to become the low level.
At this moment, if the voltage of the bit line BL is lower than that of the bit line BLB and a voltage difference between both the bit lines is small, the flip flop may output a voltage which is in the relationship reversed from the voltage relationship of the bit lines BL and BLB. In general, a minimum voltage difference between a pair of bit lines required for the flip flop to output correct data is called an offset voltage.
The offset voltage of the sense amplifier is determined by fluctuation of the threshold voltages of the transistors composing the sense amplifier. Furthermore, the offset voltage is also influenced by fluctuation of a parasitic capacitance such as wiring resistance or capacitance or asymmetry of a layout. In usual, the offset voltage of the sense amplifier is approximately 50 mV.
The sense amplifier shown in FIG. 15 will now be described in connection with the influence of the offset voltage when the sense amplifier is provided in the SRAM. The capacitance of a pair of the bit lines BL and BLB is approximately 1 pF, and a cell selected by a word line pulls out the electric charge of one of a pair of the bit lines pre-charged to a power supply voltage VDD. As a result, a very small voltage difference appears in a pair of the bit lines, and this voltage difference is amplified by the sense amplifier. At this time, assuming that the offset voltage of the sense amplifier is 50 mv, the time of 0.5 ns is required to give voltage difference of 50 mV to a pair of the bit lines as represented by the following expression (1):
1 pFxc3x9750 mV÷100 xcexcA=0.5 nsxe2x80x83xe2x80x83(1)
This time is a considerably large time for the memory which operates at a high speed, and it is important to reduce the offset voltage of the sense amplifier in order to increase the speed of the memory.
In view of the above-described problems, it is an object of the present invention to provide a semiconductor integrated circuit capable of reducing the influence of an offset voltage when amplifying and outputting a voltage in accordance with a voltage difference between first and second data lines.
To achieve this aim, there is provided a semiconductor integrated circuit comprising:
two input nodes forming a pair;
two output nodes configured to output amplification signals in accordance with a difference in signals inputted to said two input nodes; and
at least one switching circuit for switching to a specific state in order to detect an input offset voltage of said semiconductor integrated circuit before a signal to be amplified is inputted to said input node; and
said amplification signals are outputted from said two output nodes on a state that the input offset voltage of said semiconductor integrated circuit is corrected.
Further, there is provided a semiconductor integrated circuit comprising:
first and second transistors having gate terminals being connected to each other and one drain terminal being connected to the other drain terminal;
third and fourth transistors having gate terminals being connected to each other and one drain terminal being connected to the other drain terminal;
a fifth transistor connected between a connection point of said respective drain terminals of said first and second transistors and a first data line;
a sixth transistor connected between a connection point of said respective drain terminals of said third and fourth transistors and a second data line; and
an offset supply circuit configured to supply an offset voltage to at least one of said first and second data lines before turning on said fifth and sixth transistors in order to cancel out said input offset voltage of said semiconductor integrated circuit,
wherein said connection point of said respective drain terminals of said first and second transistors is connected to said respective gate terminals of said third and fourth transistors, and said respective gate terminals of said first and second transistors are connected to a connection point of the respective drain terminals of the third and fourth transistors.
Furthermore, there is provided a semiconductor integrated circuit comprising:
first and second transistors having gate terminals being connected to each other and one drain terminal being connected to the other drain terminal;
third and fourth transistors having gate terminals being connected to each other and one drain terminal being connected to the other drain terminal;
a fifth transistor connected between a connection point of said respective drain terminals of said first and second transistors and a first data line;
a sixth transistor connected between a connection point of said respective drain terminals of said third and fourth transistors and a second data line;
a seventh transistor connected between said respective gate terminals of said first and second transistors and said first data line; and
an eighth transistor connected between said respective gate terminals of said third and fourth transistors and said second data line,
wherein said connection point of said respective drain terminals of said first and second transistors is connected to said respective gate terminals of said third and fourth transistors, and said respective gate terminals of said first and second transistors are connected to said respective drain terminals of said third and fourth transistors.
Further, there is provided a semiconductor integrated circuit comprising:
first and second transistors having gate terminals being connected to each other and one drain terminal being connected to the other drain terminal;
third and fourth transistors having gate terminals being connected to each other and one drain terminal being connected to the other drain terminal;
a fifth transistor connected between a connection point of said respective drain terminals of said first and second transistors and a first data line;
a sixth transistor connected between a connection point of said respective drain terminals of said third and fourth transistors and a second data line;
a seventh transistor connected between said respective gate terminals of said first and second transistors and said first data line; and
an eighth transistor connected between said respective gate terminals of said third and fourth transistors and said second data line,
wherein said connection point of said respective drain terminals of said first and second transistors is connected to said respective gate terminals of said third and fourth transistors, and said respective gate terminals of said first and second transistors are connected to said respective drain terminals of said third and fourth transistors.
Furthermore, there is provided a semiconductor integrated circuit comprising:
first and second transistors having one source terminal being connected to the other drain terminal;
third and fourth transistors having one source terminal being connected to the other drain terminal;
a fifth transistor connected between source terminals of said second and fourth transistors and a first voltage terminal;
a sixth transistor connected between drain terminals of said first and third transistors and a second voltage terminal;
a seventh transistor connected between drain terminals of said first and third transistors and said first voltage terminal; and
an eighth transistor connected between source terminals of said second and fourth transistors and said second voltage terminal,
wherein a first data line is connected to gate terminals of said first and fourth transistors,
a second data line being connected to gate terminals of said second and third transistors.
In addition, there is provided a semiconductor integrated circuit comprising:
first and second transistors having one source terminal being connected to the other drain terminal;
third and fourth transistors having one source terminal being connected to the other drain terminal;
a fifth transistor connected between source terminals of said second and fourth transistors and a first voltage terminal;
a sixth transistor connected between drain terminals of said first and third transistors and a second voltage terminal;
a seventh transistor connected between drain terminals of said first and third transistors and said first voltage terminal; and
an eighth transistor connected between source terminals of said second and fourth transistors and said second voltage terminal,
wherein a first data line is connected to gate terminals of said first and fourth transistors,
a second data line being connected to gate terminals of said second and third transistors.
Furthermore, there is provided a semiconductor integrated circuit comprising:
first and second transistors having one source terminal connected to the other drain terminal;
third and fourth transistors having one source terminal connected to the other drain terminal;
a fifth transistor connected between said source terminals of said second and fourth transistors and a first voltage terminal;
a sixth transistor connected between said drain terminals of said first and third transistors and a second voltage terminal;
a seventh transistor connected between said source terminals of said second and fourth transistors and said second voltage terminal;
an eighth transistor having a gate terminal being connected to a gate terminal of said first transistor and having a drain terminal being connected to said source terminal of said first transistor and a gate terminal of said third transistor;
a ninth transistor having a gate terminal being connected to said gate terminal of said third transistor and having a drain terminal being connected to said source terminal of said third transistor and said gate terminal of said first transistor; and
a tenth transistor connected between source terminals of said eighth and ninth transistors and said first voltage terminal,
wherein a first data line is connected to a gate terminal of said second transistor and a second data line is connected to a gate terminal of said fourth transistor.
Furthermore, there is provided a semiconductor integrated circuit comprising:
first and second transistors having gate terminals being connected to each other and one drain terminal being connected to the other drain terminal;
third and fourth transistors having gate terminals being connected to each other and one drain terminal being connected to the other drain terminal;
a fifth transistor connected between a connection point of said both drain terminals of said first and second transistors and a first data line;
a sixth transistor connected between a connection point of said both drain terminals of said third and fourth transistors and a second data line;
a first voltage setting circuit capable of further strongly (further weakly) holding low-level voltages of said both gate terminals of said first and second transistors; and
a second voltage setting circuit capable of further strongly (further weakly) holding low-level voltage of said both gate terminals of said third and fourth transistors,
wherein said connection point of said both drain terminals of said first and second transistors is connected to said respective gate terminals of said third and fourth transistors, and said respective gate terminals of said first and second transistors are connected to said connection point of said both drain terminals of said third and fourth transistors.
According to the present invention, since an amplification signal in accordance with a difference between signals inputted to the two input nodes is outputted with a detected input offset voltage being corrected, the amplification signal is not affected by the input offset voltage.
Moreover, an offset voltage caused due to fluctuation of threshold voltages of the first to fourth transistors composing the flip flop is detected, and the voltages of the first and second data lines are corrected so as to cancel out the offset voltage. Therefore, the influence of the offset voltage can be reduced when amplifying and outputting a voltage in accordance with a voltage difference between the first and second data lines.